The development of nonvolatile memories based on the principle of trapping electrical charge in an isolated or floating gate of a field effect transistor (cell) in order to modify its turn-on threshold, has had and continues to have an extremely important role in the achievement of ever increasing levels of compactness, speed and low power consumption of integrated circuit systems. The development of such memories is closely tied to a parallel development of suitable fabrication technologies and to the physical mechanisms that can be practically exploited for injecting electrical charges in a floating gate through an isolating dielectric, which often also constitutes the gate dielectric of the cell (field effect transistor), as in the case of FLASH-EPROM cells.
The requisite of altering the content of the memory by single bytes (herein intended to constitute a unit of information composed of a certain number of bits, for example 8, 16, 32 etc.) without having to reprogram the entire memory as in the case of the so-called EPROM memories, and therefore the requisite of erasing certain selected cells while leaving unchanged the information content of other cells, has led to develop the so called EEPROM or E.sup.2 PROM cells (both being acronyms for Electrically Erasable and Programmable Read Only Memory). Typically, the problem associated with the necessity of biasing the floating gate (through its capacitive coupling with a control gate) and the semiconducting substrate to charge the floating gate and eventually discharge the electrical charge stored therein, has been satisfied by realizing a capacitive coupling zone between the floating gate and the drain region of the semiconducting substrate through a thin tunnelling oxide.
Through such a tunnelling window, the flow of electrons from the isolated gate to the drain region of the substrate and vice-versa, during an erasing and a programming phase, occurs by the so-called Fowler-Nordheim tunnelling mechanism by applying a sufficiently high voltage of one sign for erasing and of the opposite sign for the programming of the cell. Unfortunately, bytewise erasability of EPROM memories is achieved with a penalty in terms of compactness. Overall the cells are from three to four times larger for the same fabrication technology, than an EPROM cell because they require the integration of a select transistor associated with each cell.
The improvement of fabrication technologies has allowed a further reduction of the thickness of the isolation dielectric between the floating gate and the monocrystalline silicon substrate while reliably ensuring a remarkable absence of defects. This has permitted the development of the so-called FLASH-EPROM cells or memories. The FLASH cell is programmable through a mechanism of injection of hot channel electrons into the floating gate. This is achieved by biasing the control gate with a sufficiently high positive voltage and the drain of the cell with an intermediate voltage, to produce in the channel zone of the monocrystalline silicon substrate of the cell a strong electric field to generate a current of highly energetic (HOT) electrons within the silicon. The number of HOT electrons will be capable of overcoming the potential barrier at the interface with the dielectric, and be thereafter attracted toward the floating gate by the electric field.
Due to the extreme thinness of the gate dielectric layer, the erasure may be accomplished by applying a relatively high voltage to the source region while maintaining the other electrodes ground potential. Under these conditions, the electrons that had been injected into the floating gate are able to cross the thin dielectric according to a Fowler-Nordheim tunnelling mechanism, thus discharging a previously programmed floating gate.
Upon completing the memory erasure, the individual FLASH cells assume a threshold of a value that is not uniform and constant for all the cells but is normally contained within a certain variation range. In other words, there exists a spread of the threshold values among erased cells. The erasure does not take place by single bytes but rather for the entire memory block or, as often implemented, by sectors or more or less large sub-blocks.
Notwithstanding the relatively low cost, high speed and compactness of FLASH memories, there are some applications which also need, in addition to the FLASH, also a fully featured EEPROM memory block (typically of much lower capacity) in which to store data that need to be frequently altered (updated). These requisites generally occur in systems wherein only a small portion of the data stored in a permanent (nonvolatile) manner is to be frequently updated, while a vast mass of data is destined to remain unvaried in time or to be modified only at special occasions and generally after relatively long intervals of time, for example, to update the system completely to changed functioning or environmental conditions.
Alternative solutions are known offering a pseudo EEPROM performance, though substantially realizing a FLASH memory, by exploiting software methods based on momentarily shifting the data on a different media, correcting or updating them and rewriting them in the previously erased FLASH memory. These systems are relatively burdensome in terms of the time that is demanded on the system's microprocessor.
Other solutions are based upon a peculiar architecture of FLASH-EPROM arrays, such as to make them erasable by blocks. A system of this type is disclosed in the U.S. Pat. No. 5,289,423. Other proposed solutions penalize the compactness of a FLASH-EPROM memory block by also realizing a select transistor associated with each cell, for making the threshold voltage of all the cells uniform as the erasure of the memory array is performed. This technique is described in the paper entitled "A 128K FLASH-EPROM using Double Polysilicon Technology" by George Samachisa, Chien-Sheng Su, Yu-Sheng Kao, George Smarandoiu, Ting Wong, Chenming Hu, presented at the IEEE International Solid-State Circuits Conference of Feb. 25, 1987.
A further technique of this type is described in the European Patent Application No. 94830459.7 filed on Sep. 27, 1994. According to this approach, the objective is to make available some typical functions of an EEPROM cell by modifying the basic architecture of a FLASH-EPROM memory cell. By way of these structural changes of the FLASH memory, functions are obtained that are proper of an EEPROM memory (basically byte erasability and programming) with a fabrication process of FLASH memories.
An evermore accentuated development of battery powered portable devices requiring integrated systems that may be powered with extremely low voltages and having a reduced consumption, has made more severe the problems of integration compatibility of different structures. These must be optimized in terms of tolerating low supply voltages and of reducing power consumption.
FLASH memories, still unsurpassed in terms of compactness, require, during the programming phase, relatively high voltages and above all they absorb large currents. On the other hand, in single voltage supply devices the programming voltage is internally generated by charge pump circuits whose limited ability of delivering currents of non-negligible level imposes severe scaling limitations for supply voltage below approximately 2.5V.
On the other hand, the problem of containing possible energy consumption is more difficult during the reading than during programming. Indeed, in many applications, including those relative to cellular telephones, FLASH memories are reprogrammed only occasionally while conversely they are read "in continuation". Under these conditions, the target of reducing consumption may be interpreted as a target of reducing the supply voltage during the reading phase.
The requisite of assuring the highest performances with the least possible consumption, that is to say using the lowest possible supply voltage, imposes an optimization of the CMOS fabrication process and of the integrated circuit design to ensure reliable performance during reading phases with very low supply voltage and with a consequent limitation on the tolerable variation interval of the supply voltage.
According to state of the art technology, a FLASH memory specifically optimized for low consumption applications, is defined by a dual supply device, utilizing a programming voltage of approximately 2.7V to 3.6V and a reading voltage significantly lower, commonly in the range of 1.7V to 2.5V. On the other hand, as already mentioned, in many applications the capability of integrating onto the same device containing the FLASH memory a memory array (typically of reduced capacity) of EEPROM cells is desirable, that is, an EEPROM memory having unconditionally all the characteristics and peculiarities of EEPROM cells.
Though requiring a larger silicon area, EEPROM cells also require for their programming an energy that is orders of magnitude lower than that needed by high density FLASH-EPROM cells. In other words, EEPROM cells even though requiring programming voltages relatively high, absorb currents relatively much lower than those required by high density FLASH-EPROM cells. Therefore, the high programming voltage can be more easily generated internally to the integrated device with acceptable yields by means of dedicated charge pump circuits even if starting from a relatively low supply voltage. An integrated circuit containing a high density FLASH memory and a fully featured EEPROM memory, normally functioning with a voltage from approximately 1.7 to 2.5V during reading phases of both the types of memory, as well as during programming phases of the EEPROM cells, and with a supply voltage from 2.7V to 3.6V for the programming of the high density FLASH memory, represents, according to present technology, a nearly optimal condition for applications in portable instrumentation such as cellular telephones.
The structure of a FLASH high density memory cell is that of a single transistor having a gate structure including double polysilicon levels as shown in FIG. 1. The cell may be programmed either through injection of hot channel electrons or by means of the Fowler-Nordheim tunnelling mechanism and is erased through a Fowler-Nordheim tunnelling mechanism. In all cases the programming efficiency is rather low because only a small portion of the current absorbed during the writing phase is exploited for charging or discharging the floating gate while the majority of it is sinked toward the substrate or the cell's source, as shown in FIG. 2.
An EEPROM cell has a more complex structure, including three elements: a double gate transistor, a tunnelling window defined by a thin area of tunnelling oxide realized in an overlap region of the same floating gate over an N-type diffusion, and a select transistor. The cell is written and erased through the Fowler-Nordheim and it is important to observe that, differently from the FLASH cell, practically the entire amount of absorbed current during the writing phase of the cell is exploited for charging the floating gate.
Despite the fact that both types of cells may have an overlapped multilevel gate structure, realized with two polysilicon levels, as well as the fact that both utilize a relatively thin tunnelling dielectric layer (tunnel oxide), it is quite difficult, that is, extremely expensive to integrate both on the same chip because of the different thickness that are required for the two tunnelling dielectric layers (tunnel oxide). The tunnelling dielectric of a FLASH-EPROM cell has a thickness commonly within 9 and 12 nm, grown over a substantially undoped silicon (that is to say on a channel region of the semiconductor of a two gate transistor). In contrast, the tunnelling dielectric layer of an EEPROM cell has commonly a thickness of 7 to 9 nm, grown over an N-type doped silicon region. As well known to those skilled in the art, the rate of growth of an oxide layer is definitely higher over an N-type doped region of the silicon semiconductor substrate than over an undoped or significantly less doped region of the same substrate.
From this stems the difficulty or impracticality of simultaneously growing both the oxides. It should be considered that, according to state of the art technologies, the growing of a certain gate dielectric layer (or tunnel dielectric layer) must be immediately followed by the deposition of a relative polysilicon layer of capacitive coupling through the dielectric just formed.
In most recent fabrication processes of high density FLASH memory devices, based on the programming mechanism via hot channel electron injection or via a dual Fowler-Noroheim tunnelling (for programming and erasing), a special CMOS structure referred to as "triple well" structure as shown in FIG. 3, is used so to allow the integration of either P-MOS transistors or N-MOS transistors isolated from the p-substrate. This facilitates the generation and switching of the negative voltages required during the writing phase (programming) of the FLASH memory cells. In these processes use is made of two different gate oxide layers for the peripheral transistors: a relatively thick layer, usually of about 15-25 nm, is used for peripheral transistors of the decoding circuits subject to high programming voltages, whereas a thinner gate layer is used for the other peripheral transistors destined to function at lower supply voltages.
The thickness of the gate oxide of these "low voltage" transistors, scaled in relation with the actual design reading voltage, is usually within about 15 and 18 nm for "5V devices" and is generally within about 10 and 12 nm for "3V devices". In the case of a reading supply voltage between 1.7V and 2.5V the optimal thickness of the gate oxide of peripheral low voltage transistors may be estimated to be between 5 and 7 nm approximately.